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Espressif Systems /ESP32-S2 /UHCI0 /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_START_INT_ST)RX_START_INT_ST 0 (TX_START_INT_ST)TX_START_INT_ST 0 (RX_HUNG_INT_ST)RX_HUNG_INT_ST 0 (TX_HUNG_INT_ST)TX_HUNG_INT_ST 0 (IN_DONE_INT_ST)IN_DONE_INT_ST 0 (IN_SUC_EOF_INT_ST)IN_SUC_EOF_INT_ST 0 (IN_ERR_EOF_INT_ST)IN_ERR_EOF_INT_ST 0 (OUT_DONE_INT_ST)OUT_DONE_INT_ST 0 (OUT_EOF_INT_ST)OUT_EOF_INT_ST 0 (IN_DSCR_ERR_INT_ST)IN_DSCR_ERR_INT_ST 0 (OUT_DSCR_ERR_INT_ST)OUT_DSCR_ERR_INT_ST 0 (IN_DSCR_EMPTY_INT_ST)IN_DSCR_EMPTY_INT_ST 0 (OUTLINK_EOF_ERR_INT_ST)OUTLINK_EOF_ERR_INT_ST 0 (OUT_TOTAL_EOF_INT_ST)OUT_TOTAL_EOF_INT_ST 0 (SEND_S_REG_Q_INT_ST)SEND_S_REG_Q_INT_ST 0 (SEND_A_REG_Q_INT_ST)SEND_A_REG_Q_INT_ST 0 (DMA_INFIFO_FULL_WM_INT_ST)DMA_INFIFO_FULL_WM_INT_ST

Description

Masked interrupt status

Fields

RX_START_INT_ST

This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1.
TX_START_INT_ST

This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1.
RX_HUNG_INT_ST

This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1.
TX_HUNG_INT_ST

This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1.
IN_DONE_INT_ST

This is the masked interrupt bit for UHCI_IN_DONE_INT interrupt when UHCI_IN_DONE_INT_ENA is set to 1.
IN_SUC_EOF_INT_ST

This is the masked interrupt bit for UHCI_IN_SUC_EOF_INT interrupt when UHCI_IN_SUC_EOF_INT_ENA is set to 1.
IN_ERR_EOF_INT_ST

This is the masked interrupt bit for UHCI_IN_ERR_EOF_INT interrupt when UHCI_IN_ERR_EOF_INT_ENA is set to 1.
OUT_DONE_INT_ST

This is the masked interrupt bit for UHCI_OUT_DONE_INT interrupt when UHCI_OUT_DONE_INT_ENA is set to 1.
OUT_EOF_INT_ST

This is the masked interrupt bit for UHCI_OUT_EOF_INT interrupt when UHCI_OUT_EOF_INT_ENA is set to 1.
IN_DSCR_ERR_INT_ST

This is the masked interrupt bit for UHCI_IN_DSCR_ERR_INT interrupt when UHCI_IN_DSCR_ERR_INT is set to 1.
OUT_DSCR_ERR_INT_ST

This is the masked interrupt bit for UHCI_OUT_DSCR_ERR_INT interrupt when UHCI_OUT_DSCR_ERR_INT_ENA is set to 1.
IN_DSCR_EMPTY_INT_ST

This is the masked interrupt bit for UHCI_IN_DSCR_EMPTY_INT interrupt when UHCI_IN_DSCR_EMPTY_INT_ENA is set to 1.
OUTLINK_EOF_ERR_INT_ST

This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1.
OUT_TOTAL_EOF_INT_ST

This is the masked interrupt bit for UHCI_OUT_TOTAL_EOF_INT interrupt when UHCI_OUT_TOTAL_EOF_INT_ENA is set to 1.
SEND_S_REG_Q_INT_ST

This is the masked interrupt bit for UHCI_SEND_S_REG_Q_INT interrupt when UHCI_SEND_S_REG_Q_INT_ENA is set to 1.
SEND_A_REG_Q_INT_ST

This is the masked interrupt bit for UHCI_SEND_A_REG_Q_INT interrupt when UHCI_SEND_A_REG_Q_INT_ENA is set to 1.
DMA_INFIFO_FULL_WM_INT_ST

This is the masked interrupt bit for UHCI_DMA_INFIFO_FULL_WM_INT INTERRUPT when UHCI_DMA_INFIFO_FULL_WM_INT_ENA is set to 1.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data